Sometimes the need
arises to construct a really simple oscillator. This could hardly be
simpler than the circuit shown here, which uses just three components,
and offers five separate octaves, beginning around Middle C (Stage 14).
Octave # 5 is missing, due to the famous (or infamous) missing Stage 11
of the 4060B IC. We might call this a Colpitts ‘L’ oscillator, without
the ‘C’. Due to the reactance of the 100-µH inductor and the propagation
delay of the internal oscillator, oscillation is set up around 5 MHz.
When this is divided down, Stage 14 approaches the frequency of Middle C
(Middle C = 261.626 Hz).
Stages 13, 12, 10, and 9 provide higher octaves, with Stages 8 to 4
being in the region of ultrasound. If the oscillator’s output is taken
to the aerial of a Medium Wave Radio, L1 may serve as the search coil of
a Pipe Locator, with a range of about 50 mm. This is tuned by finding a
suitable heterodyne (beat note) on the medium wave band. In that case,
piezo sounder Bz1 is omitted. The Simple Oscillator / Pipe Locator draws
around 7mA from a 9-12 V DC source.
The 32-kHz low-power
clock oscillator offers numerous advantages over conventional oscillator
circuits based on a CMOS inverter. Such
inverter circuits present problems, for example, supply currents
fluctuate widely over a 3V to 6V supply range, while current consumption
below 250 µA is difficult to attain. Also, operation can be unreliable
with wide variations in the supply voltage and the inverter’s input
characteristics are subject to wide tolerances and differences among
manufacturers. The circuit shown here solves the above problems. Drawing
just 13 µA from a 3V supply, it consists of a one-transistor
amplifier/oscillator (T1) and a low-power comparator/reference device
Very Low Power 32kHz Oscillator Circuit Diagram
The base of T1 is biased at 1.25 V using R5/R4 and the reference in
IC1. T1 may be any small-signal transistor with a decent beta of 100 or
so at 5 µA (defined here by R3, fixing the collector voltage at about 1 V
below Vcc). The amplifier’s nominal gain is approximately 2 V/V. The
quartz crystal combined with load capacitors C1 and C3 forms a feedback
path around T1, whose 180 degrees of phase shift causes the oscillation.
The bias voltage of 1.25 V for the comparator inside the MAX931 is
defined by the reference via R2. The comparator’s input swing is thus
accurately centred around the reference voltage.
Operating at 3 V and 32 kHz, IC1 draws just 7 µA. The comparator
output can source and sink 40 mA and 5 mA respectively, which is ample
for most low-power loads. However, the moderate rise/fall times of 500
ns and 100 ns respectively can cause standard, high-speed CMOS
logic to draw higher than usual switching currents. The optional 74HC14
Schmitt trigger shown at the circuit output can handle the comparator’s
rise/fall times with only a small penalty in supply current.
This circuit was developed to allow watch crystals to be used in an existing CMOS
oscillator circuit that was to run from a 12V supply. The problem is
that these crystals only work up to a supply voltage of about 6V. Any
more than that and the crystal will be over-driven, causing it to
shatter. This circuit solves the problem by using LEDs
1 & 2 and a 470nF capacitor (C3) to limit the drive to the crystal
to about 4V peak-to-peak. Note that it may be necessary to adjust C1
& C2 to ensure reliable start-up and stable oscillation with some
crystals. However, the C1:C2 ratio should be maintained. As a bonus, the
two LEDs both glow, giving a visual indication that the oscillator is working.
Safe Oscillator Circuit Diagram For Watch Crystals
The relatively high values used here for capacitors C1 & C2 will
load the crystal, which means that the oscillator will run at less than
the nominal crystal frequency (32.768kHz).
Author: Duncan Graham – Copyright: Silicon Chip Electronics
The oscillator shown in
Figure1 is frequently used in digital circuits and may, therefore, look
very familiar. Many readers may not know that this type of oscillator
suffers from a nasty draw-back caused by noise. When the amplitude of
the noise is higher than the hysteresis of the gates used for the
oscillator, spurious switching pulses are generated near the zero
crossings. This problem can be cured only by ensuring that the rise time
of the input signal is shorter than the reaction time of the relevant
gate. When the oscillator is built with fast logic gates, such as those
in the HC-series, the like-lihood of the problem occurring is great.
However, as long as the positive feedback is fast enough, nothing
untoward will happen. However, when delays occur owing to the transit
time of the components used, the problem may rear its head. In the
configuration of Figure 1a, the signal passes through two inverters and
thus experiences twice the transit time of a single gate. The upper
signal in the oscilloscope trace in Figure 2 shows the result of this:
the gates used are simply too fast for this type of oscillator. If one
of the inverters is replaced by a buffer, and the oscillator is modified
as shown in Figure 1b, the transit time is limited to that of one gate:
the lower trace in Figure 2 shows that the oscillator then works
correctly. The practical circuit diagram of the general-purpose
oscillator is shown in Figure 3. Note that two XOR gates are used to ensure that the transit time of the buffer is equal to that of the inverter.
This simple LED
torch is driven by a 2-transistor blocking oscillator which steps up
the voltage from a 1.5V cell. It relies on the inherent current limiting
of the 150µH choke to protect the white LED from over-drive. With a 9V zener diode in place of the white LED, it could also provide a 9V supply provided the current drain is modest.
Author: Peter Goodwin
Copyright: Silicon Chip Electronics
Nowadays, it is no longer necessary to use
discrete components to build oscillators. Instead, many manufacturers
provide ready-made voltage-controlled oscillator (VCO)
ICs that need only a few frequency-determining external components. One
example is the RF Micro Devices RF2506. This IC operates with a supply
voltage between 2.7 and 3.6 V (3.3V nominal) and provides a low-noise
oscillator transistor with integrated DC bias setting. In addition, it
has an isolating buffer amplifier that strongly reduces the effects of
load variations (load pulling) on the oscillator. If a voltage less than
0.7V is applied to the power-down input (pin 8), the oscillator is shut
down and the current consumption drops from 9mA to less than 1µA. The VCO is enabled when the voltage on pin 8 is at least +3V.
Connecting the feedback capacitors C1 and C2 to pins 3 (FDBK) and 4 (VTUNE)
transforms the internal transistor into a Colpitts oscillator. A
resonator is also needed; here this consists of C4 and L1, and it is
coupled via C3. Keep the Q factor of the coil as high as possible (by
using an air-core coil, for example), to ensure a low level of phase
noise. Since most applications require a tuneable oscillator, the
varicap diode D1 (BBY40, BBY51, BB804 etc) can be used to adjust the
resonant frequency. The tuning voltage UTune is applied via a high
resistance. The value of the tuning voltage naturally depends on the
desired frequency range and the variable-capacitance diode (D1) that is
used. The table shows a number of suggestions for selecting the
frequency-determining components. If the frequency range is narrow, a
parallel-resonant circuit should be connected between the output pin and
+Vcc, to form the collector load for the output transistor.
This can be built using the same components as the oscillator resonator. With a broadband VCO,
use a HF choke instead, with a value of a few microhenries to a few
nanohenries, depending on the frequency band. In this case C6 is not
needed. The output level of this circuit is –3dBm with an LC load and –7
dBm with a choke load. The table that accompanies the schematic diagram
provides rough indications of component values for various frequencies.
It is intended to provide a starting point for experimentation. The
coupling between the variable-capacitance diode and C5 determines the
tuning range of the VCO. The manufacturer maintains an Internet site at http://www.rfmd.com, where you can ﬁnd more information about this interesting oscillator IC.
Although a simple
crystal oscillator may be built from one comparator of an LT1720/LT1721,
this will suffer from a number of inherent shortcomings and design
problems. Although the LT1720/LT1721 will give the correct logic output
when one input is outside the common mode range, additional delays may
occur when it is so operated, opening the possibility of spurious
operating modes. Therefore, the DC bias voltages at the inputs have to
be set near the center of the LT1720/LT1721’s common mode range and a
resistor is required to attenuate the feedback to the non-inverting
input. Unfortunately, although the output duty cycle for this circuit is
roughly 50%, it is affected by resistor tolerances and, to a lesser
extent, by comparator offsets and timings.
If a 50% duty cycle is required, the circuit shown here creates a
pair of complementary outputs with a forced 50% duty cycle. Crystals are
narrow-band elements, so the feedback to the non-inverting input is a
ﬁltered analogue version of the square-wave output. The crystal’s path
provides resonant positive feedback and stable oscillation occurs.
Changing the non-inverting reference level can vary the duty cycle. The
2k-680Ω resistor pair sets a bias point at the comparator + (Comparator
IC1a) and – (Comparator IC1b) input. At the complementary input of each
comparator, the 2k-1.8k-0.1µF path sets up an appropriate DC average
level based on the output.
IC1b creates a complementary output to IC1a by comparing the same
two nodes with the opposite input. IC2 compares band-limited versions of
the outputs and biases IC1a’s negative input. IC1a’s only degree of
freedom to respond is variation of pulse width; hence the outputs are
forced to 50% duty cycle. The circuit operates from 2.7V to 6V. When
‘scoping the oscillator output signal, a slight dependence on comparator
loading, will be noted, so equal and resistive loading should be used
in critical applications. The circuit works well because of the two
matched delays and rail-to-rail outputs of the LT1720.
The National Physics Laboratory broadcasts a time signal, previously known as the Rugby clock but now called "Time from NPL." Its most commonly known as the MSF signal due to it originally being identified in Morse code those letters. It is broadcast from Anthorn on 60kHz. Many commercial clocks use it to automatically set themselves.
I decided to convert a digital clock I bought into one set by the MSF signal. To make the project more interesting I decided to use the ATtiny2313 microcontroller with only 2k flash ROM and 128 bytes of RAM.
– Automatically set by MSF time signal
– Bright, flicker free display
– Alarm with choice of 5 polyphonic melodies
– Hour chime with choice of melodies and no chime between 00:00 and 08:00
The original clock electronics used two PCBs, one for the 7 segment LEDs and another for the clock controller and support hardware. I started by tracing the connections between them and mapping out how the display worked.
The display is multiplexed with simple transistor switches for the common anode. Only the middle two 7 segment displays have dots. I connected the anode transistors to the AVR with 2k2 resistors to limit current and the cathodes to a 74HC595 shift register via a ULN2803 Darlington array. I removed the controller IC and all other unused parts.
The AVR uses a 12MHz crystal which is accurate enough for keeping time. In my initial tests on the bench it varied by less than one second per day, but when installed in the clock case it looses about 3-4 seconds over 24 hours. Since the time is re-synchronised with the MSF signal every night that is more than adequate.
An MSF receiver module is connected to the AVR. I bought it for a few pounds and it works very well, although like most low frequency time code receivers it is extremely sensitive to noise. The multiplexed display has to be turned off while it is in use, so it is not possible to see the current time when it is being re-synchronised. I had to use a long USB cable for programming during development because the electrical noise from my PC was interfering.
Download Schematic in PDF
Notes on schematic:
T1-T4: Select a suitable PNP transistor for the 7 segment displays. I used 2N3906s and 2k2 resistors.
C1-C2: Depends on the crystal you use, 22pF is usually suitable.
R3-R10: Depends on the current required for the LEDs, the original circuit used 100Ω so I stuck with them for R3-R9. R10 has to be 470Ω to make the dot match the brightness of the bars.
Because the ATtiny2313 only has 2k of flash ROM the code was written in assembler and is quite efficient. Even so I eventually ran out of code space and had to remove some of the debugging output. There are still space savings to be made but the clock is feature-complete.
ATtiny2313 memory use summary [bytes]:Segment BeginEndCode Data UsedSize Use%-------------------------------------------------------------[.cseg] 0x000000 0x0007f8 2006 34 2040204899.6%[.dseg] 0x000060 0x000060000 128 0.0%[.eseg] 0x000000 0x000000000 128 0.0%
Time keeping is via an interrupt that also handles display multiplexing. The display is multiplexed at 100Hz which translates to a 400Hz timer interrupt (4 digits x 100Hz). The interrupt also sends signals back to the main code when minutes and hours increment.
Oscilloscope trace of MSF signal
The MSF protocol represents binary bits with differing length pulses which are generated by switching the carrier signal on and off. The main two are 100ms (zero) and 200ms (one). The start of a minute is signaled with a 500ms pulse and towards the end of the minute cycle the parity bits can be 300ms long.
| MSF bit
|| Start of Minute Marker
|| 500ms pulse
|| DUT1 offset
|| 8 bit BCD 00..99
|| 5 bit BCD 01..12
|| Day of Month
|| 6 bit BCD 01..31
|| Day of Week
|| 3 bit BCD 1..7
|| 6 bit BCD 00..23
|| 7 bit BCD 00..59
|| End of Minute Marker
|| Always 0
|| BST change warning
|| 1 bit flag
|| Year Parity
|| Odd parity bits 17..24
|| Month Parity
|| Odd parity bits 25..35
|| Day of Week Parity
|| Odd parity bits 36..38
|| Time Parity
|| Odd parity bits 39..51
|| BST flag
|| 1 bit flag
|| Always 0
For details of the data format the Wikipedia page has some information about the signal which is mostly correct. The NPL documentation is also quite useful.
MSF reception requires fault tolerant code. Even under ideal conditions the signal is likely to contain noise. The decoded signal also has to be validated before being accepted.
The MSF reception routine waits for a pulse to start and then measures the length using a 100Hz timer. It rejects pulses (or drop-outs) of less than 5ms as noise. There is ±20ms leeway when decoding pulse lengths.
Once one complete minute’s worth of pluses have been received they are decoded, sanity checked and parity checked. If the signal looks valid then the decoded data is stored and a second signal is received. If that second signal also passes all checks and gives a time exactly one minute after the first then it is deemed correct and the clock synchronised.
Synchronisation takes place when the clock is first powered on and again at 3AM every night. 3AM was chosen to avoid inconveniencing the user and because there is less RF interference at night.
A note about MSF signal accuracy. The broadcast time is supposed to be within 1ms of UTC. However, there is propogation delay between the transmitter and the receiver which cannot easily be measured or removed automatically. Based on where I live I estimate the delay to be around 275ms. GPS time compensates for this delay.
The clock is controlled by three buttons on the back. Since the clock uses the MSF signal to set itself automatically there is no way to set it manually. In any case there is not enough free flash memory to implement a time setting interface.
Holding down the SET button for one second enters setting mode. The UP/DOWN buttons change the setting and SET advances to the next one. The sequence is:
1. Alarm on/off
2. Alarm hour
3. Alarm minute
4. Alarm melody
5. Hour chime on/off
6. Hour chime melody
Buttons are debounced and repeat when held.
I had planned to make the ATtiny2313 generate alarm melodies and hour chimes, but there was not enough code space left. I decided to modify ChaN’s Wavetable Melody Generator and control it with the 2313. ChaN is a bit of a genius when it comes to implementing things like this in an efficient yet flexible way with a minimum of external hardware required. In fact his WGM only requires an ATtiny45, speaker and power supply to work.
The requirements for the Melody Generator were multiple melodies and chimes. I decided to use music and sounds from Japan Rail (JR) stations. Probably only a 鉄道ファン, can understand why 🙂
I started by creating a new wavetable (actually there is only one instrument so it isn’t really a "table"…) using a sample from the default TiMidity++ set. It had to be cut into two sections, the attack and sustain phases. Typically instruments that are percussive (e.g. pianos, bells, chimes) create a sudden transient sound when hit where the waveforms are non-symmetrical called the attack. They then quickly start to oscillate and fade out as energy is lost, called the sustain. Because the oscillating part of the sound is simply the same waveform repeated with ever decreasing magnitude it is only necessary to store one cycle and reduce its amplitude to zero over the length of the sustain period. This method also makes it easy to vary the length of the sustain.
I found MIDI versions of the melodies and chines I wanted and converted them to text with MIDINOTE. The text was then imported into Excel, re-exported to text in a more suitable format and cleaned up in Notepad++. Finally ChaN’s Perl script was used to convert them to AVR assembler include files.
ChaN’s code was altered to support multiple scores, each with it’s own sustain decay rate. I also added some code to interface the ATtiny45 with the main ATtiny2313 using a very simple protocol. The 2313 pulls an enable line low and then pulses a data line a number of times corresponding to the score it wants to have played.
The hardware is trivial – merely an 8Ω speaker connected directly to the AVR.
Download MSF Clock Source
Download Melody Generator